`timescale 1ns / 1ps
`include "ahb_slave.v"
`include "ahb_slave_ram.v"
`include "ahb_slave_mem.v"
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: Vakerlis Christos
// 
// Create Date:    23:03:44 05/12/2014 
// Design Name: 
// Module Name:    ahb_3_6 
// Project Name: ahb_3(masters)_6(slaves)
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ahb_3_6(clk,reset,M0_HADDR,M1_HADDR,M2_HADDR,M0_HBURST,M1_HBURST,M2_HBURST,
	      M0_HSIZE,M1_HSIZE,M2_HSIZE,M0_HTRANS,M1_HTRANS,M2_HTRANS,M0_HWRITE,M1_HWRITE,M2_HWRITE,
	      M0_HWDATA,M1_HWDATA,M2_HWDATA,M0_HRDATA,M1_HRDATA,M2_HRDATA,M0_HREADY,M1_HREADY,M2_HREADY,M0_HRESP,M1_HRESP,M2_HRESP,
             S0_HADDR,S1_HADDR,S2_HADDR,S3_HADDR,S4_HADDR,S5_HADDR,
             S0_HBURST,S1_HBURST,S2_HBURST,S3_HBURST,S4_HBURST,S5_HBURST,
             S0_HSIZE,S1_HSIZE,S2_HSIZE,S3_HSIZE,S4_HSIZE,S5_HSIZE,
             S0_HTRANS,S1_HTRANS,S2_HTRANS,S3_HTRANS,S4_HTRANS,S5_HTRANS,
             S0_HWRITE,S1_HWRITE,S2_HWRITE,S3_HWRITE,S4_HWRITE,S5_HWRITE,
             S0_HWDATA,S1_HWDATA,S2_HWDATA,S3_HWDATA,S4_HWDATA,S5_HWDATA,
             S0_HRDATA,S1_HRDATA,S2_HRDATA,S3_HRDATA,S4_HRDATA,S5_HRDATA,
             S0_HREADY,S1_HREADY,S2_HREADY,S3_HREADY,S4_HREADY,S5_HREADY,
             S0_HRESP,S1_HRESP,S2_HRESP,S3_HRESP,S4_HRESP,S5_HRESP

 );
	input                      clk;
   input                      reset;
//	input                      STALL_pre;
    output [31:0]      		M0_HADDR,M1_HADDR,M2_HADDR;
   output [2:0]       		M0_HBURST,M1_HBURST,M2_HBURST;
   output [1:0]       		M0_HSIZE,M1_HSIZE,M2_HSIZE;
   output [1:0]       		M0_HTRANS,M1_HTRANS,M2_HTRANS;
   output             		M0_HWRITE,M1_HWRITE,M2_HWRITE;
   output [31:0]      		M0_HWDATA,M1_HWDATA,M2_HWDATA;
   output [31:0]       		M0_HRDATA,M1_HRDATA,M2_HRDATA;
   output              		M0_HREADY,M1_HREADY,M2_HREADY;
   output              		M0_HRESP,M1_HRESP,M2_HRESP;
	 

   output [31:0]               S0_HADDR,S1_HADDR,S2_HADDR,S3_HADDR,S4_HADDR,S5_HADDR;
   output [2:0]                S0_HBURST,S1_HBURST,S2_HBURST,S3_HBURST,S4_HBURST,S5_HBURST;
   output [1:0]                S0_HSIZE,S1_HSIZE,S2_HSIZE,S3_HSIZE,S4_HSIZE,S5_HSIZE;
   output [1:0]                S0_HTRANS,S1_HTRANS,S2_HTRANS,S3_HTRANS,S4_HTRANS,S5_HTRANS;
   output                      S0_HWRITE,S1_HWRITE,S2_HWRITE,S3_HWRITE,S4_HWRITE,S5_HWRITE;
   output [31:0]               S0_HWDATA,S1_HWDATA,S2_HWDATA,S3_HWDATA,S4_HWDATA,S5_HWDATA;
   output [31:0]              S0_HRDATA,S1_HRDATA,S2_HRDATA,S3_HRDATA,S4_HRDATA,S5_HRDATA;
   output                     S0_HREADY,S1_HREADY,S2_HREADY,S3_HREADY,S4_HREADY,S5_HREADY;
   output                     S0_HRESP,S1_HRESP,S2_HRESP,S3_HRESP,S4_HRESP,S5_HRESP;
	

	master2 #(0) Master0 (
		.clk(clk), 
		.reset(reset), 
		.HBURST(M0_HBURST), 
		.HSIZE(M0_HSIZE), 
		.HADDR(M0_HADDR), 
		.HTRANS(M0_HTRANS), 
		.HWRITE(M0_HWRITE), 
		.HWDATA(M0_HWDATA), 
		.HRDATA(M0_HRDATA), 
		.HREADY(M0_HREADY), 
		.HRESP(M0_HRESP)
	);
	
	master2 #(1) Master1 (
		.clk(clk), 
		.reset(reset), 
		.HBURST(M1_HBURST), 
		.HSIZE(M1_HSIZE), 
		.HADDR(M1_HADDR), 
		.HTRANS(M1_HTRANS), 
		.HWRITE(M1_HWRITE), 
		.HWDATA(M1_HWDATA), 
		.HRDATA(M1_HRDATA), 
		.HREADY(M1_HREADY), 
		.HRESP(M1_HRESP)
	);

	master2 #(2) Master2 (
		.clk(clk), 
		.reset(reset), 
		.HBURST(M2_HBURST), 
		.HSIZE(M2_HSIZE), 
		.HADDR(M2_HADDR), 
		.HTRANS(M2_HTRANS), 
		.HWRITE(M2_HWRITE), 
		.HWDATA(M2_HWDATA), 
		.HRDATA(M2_HRDATA), 
		.HREADY(M2_HREADY), 
		.HRESP(M2_HRESP)
	);
	
	
	ahb_slave Slave0 (
		.clk(clk), 
		.reset(reset), 
		.HSEL(S0_HTRANS[1]), 
		.HADDR(S0_HADDR), 
		.HBURST(S0_HBURST), 
		.HSIZE(S0_HSIZE), 
		.HTRANS(S0_HTRANS), 
		.HWRITE(S0_HWRITE), 
		.HWDATA(S0_HWDATA), 
		.HRDATA(S0_HRDATA), 
		.HREADY(S0_HREADY), 
		.HRESP(S0_HRESP), 
		.STALL_pre(S0_HTRANS[1])
	);
	

	ahb_slave Slave1 (
		.clk(clk), 
		.reset(reset), 
		.HSEL(S1_HTRANS[1]), 
		.HADDR(S1_HADDR), 
		.HBURST(S1_HBURST), 
		.HSIZE(S1_HSIZE), 
		.HTRANS(S1_HTRANS), 
		.HWRITE(S1_HWRITE), 
		.HWDATA(S1_HWDATA), 
		.HRDATA(S1_HRDATA), 
		.HREADY(S1_HREADY), 
		.HRESP(S1_HRESP), 
		.STALL_pre(S1_HTRANS[1])
	);
	
	ahb_slave Slave2 (
		.clk(clk), 
		.reset(reset), 
		.HSEL(S2_HTRANS[1]), 
		.HADDR(S2_HADDR), 
		.HBURST(S2_HBURST), 
		.HSIZE(S2_HSIZE), 
		.HTRANS(S2_HTRANS), 
		.HWRITE(S2_HWRITE), 
		.HWDATA(S2_HWDATA), 
		.HRDATA(S2_HRDATA), 
		.HREADY(S2_HREADY), 
		.HRESP(S2_HRESP), 
		.STALL_pre(S2_HTRANS[1])
	);

	ahb_slave Slave3 (
		.clk(clk), 
		.reset(reset), 
		.HSEL(S3_HTRANS[1]), 
		.HADDR(S3_HADDR), 
		.HBURST(S3_HBURST), 
		.HSIZE(S3_HSIZE), 
		.HTRANS(S3_HTRANS), 
		.HWRITE(S3_HWRITE), 
		.HWDATA(S3_HWDATA), 
		.HRDATA(S3_HRDATA), 
		.HREADY(S3_HREADY), 
		.HRESP(S3_HRESP), 
		.STALL_pre(S3_HTRANS[1])
	);

	ahb_slave Slave4 (
		.clk(clk), 
		.reset(reset), 
		.HSEL(S4_HTRANS[1]), 
		.HADDR(S4_HADDR), 
		.HBURST(S4_HBURST), 
		.HSIZE(S4_HSIZE), 
		.HTRANS(S4_HTRANS), 
		.HWRITE(S4_HWRITE), 
		.HWDATA(S4_HWDATA), 
		.HRDATA(S4_HRDATA), 
		.HREADY(S4_HREADY), 
		.HRESP(S4_HRESP), 
		.STALL_pre(S4_HTRANS[1])
	);
	
	ahb_slave Slave5 (
		.clk(clk), 
		.reset(reset), 
		.HSEL(S5_HTRANS[1]), 
		.HADDR(S5_HADDR), 
		.HBURST(S5_HBURST), 
		.HSIZE(S5_HSIZE), 
		.HTRANS(S5_HTRANS), 
		.HWRITE(S5_HWRITE), 
		.HWDATA(S5_HWDATA), 
		.HRDATA(S5_HRDATA), 
		.HREADY(S5_HREADY), 
		.HRESP(S5_HRESP), 
		.STALL_pre(S5_HTRANS[1])
	);
	
	ahb_matrix_3_6 ahb_matrix(
		.clk(clk), 
		.reset(reset), 
		.M0_HADDR(M0_HADDR), 
		.M0_HBURST(M0_HBURST), 
		.M0_HSIZE(M0_HSIZE), 
		.M0_HTRANS(M0_HTRANS), 
		.M0_HWRITE(M0_HWRITE), 
		.M0_HWDATA(M0_HWDATA), 
		.M0_HRDATA(M0_HRDATA), 
		.M0_HRESP(M0_HRESP), 
		.M0_HREADY(M0_HREADY), 
		.M1_HADDR(M1_HADDR), 
		.M1_HBURST(M1_HBURST), 
		.M1_HSIZE(M1_HSIZE), 
		.M1_HTRANS(M1_HTRANS), 
		.M1_HWRITE(M1_HWRITE), 
		.M1_HWDATA(M1_HWDATA), 
		.M1_HRDATA(M1_HRDATA), 
		.M1_HRESP(M1_HRESP), 
		.M1_HREADY(M1_HREADY), 
		.M2_HADDR(M2_HADDR), 
		.M2_HBURST(M2_HBURST), 
		.M2_HSIZE(M2_HSIZE), 
		.M2_HTRANS(M2_HTRANS), 
		.M2_HWRITE(M2_HWRITE), 
		.M2_HWDATA(M2_HWDATA), 
		.M2_HRDATA(M2_HRDATA), 
		.M2_HRESP(M2_HRESP), 
		.M2_HREADY(M2_HREADY), 
		.S0_HADDR(S0_HADDR), 
		.S0_HBURST(S0_HBURST), 
		.S0_HSIZE(S0_HSIZE), 
		.S0_HTRANS(S0_HTRANS), 
		.S0_HWRITE(S0_HWRITE), 
		.S0_HWDATA(S0_HWDATA), 
		.S0_HRDATA(S0_HRDATA), 
		.S0_HRESP(S0_HRESP), 
		.S0_HREADY(S0_HREADY), 
		.S1_HADDR(S1_HADDR), 
		.S1_HBURST(S1_HBURST), 
		.S1_HSIZE(S1_HSIZE), 
		.S1_HTRANS(S1_HTRANS), 
		.S1_HWRITE(S1_HWRITE), 
		.S1_HWDATA(S1_HWDATA), 
		.S1_HRDATA(S1_HRDATA), 
		.S1_HRESP(S1_HRESP), 
		.S1_HREADY(S1_HREADY), 
		.S2_HADDR(S2_HADDR), 
		.S2_HBURST(S2_HBURST), 
		.S2_HSIZE(S2_HSIZE), 
		.S2_HTRANS(S2_HTRANS), 
		.S2_HWRITE(S2_HWRITE), 
		.S2_HWDATA(S2_HWDATA), 
		.S2_HRDATA(S2_HRDATA), 
		.S2_HRESP(S2_HRESP), 
		.S2_HREADY(S2_HREADY), 
		.S3_HADDR(S3_HADDR), 
		.S3_HBURST(S3_HBURST), 
		.S3_HSIZE(S3_HSIZE), 
		.S3_HTRANS(S3_HTRANS), 
		.S3_HWRITE(S3_HWRITE), 
		.S3_HWDATA(S3_HWDATA), 
		.S3_HRDATA(S3_HRDATA), 
		.S3_HRESP(S3_HRESP), 
		.S3_HREADY(S3_HREADY), 
		.S4_HADDR(S4_HADDR), 
		.S4_HBURST(S4_HBURST), 
		.S4_HSIZE(S4_HSIZE), 
		.S4_HTRANS(S4_HTRANS), 
		.S4_HWRITE(S4_HWRITE), 
		.S4_HWDATA(S4_HWDATA), 
		.S4_HRDATA(S4_HRDATA), 
		.S4_HRESP(S4_HRESP), 
		.S4_HREADY(S4_HREADY), 
		.S5_HADDR(S5_HADDR), 
		.S5_HBURST(S5_HBURST), 
		.S5_HSIZE(S5_HSIZE), 
		.S5_HTRANS(S5_HTRANS), 
		.S5_HWRITE(S5_HWRITE), 
		.S5_HWDATA(S5_HWDATA), 
		.S5_HRDATA(S5_HRDATA), 
		.S5_HRESP(S5_HRESP), 
		.S5_HREADY(S5_HREADY)
	);

	 

endmodule


